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? 2012 microchip technology inc. preliminary ds41668a-page 1 mtch112 features: ? capacitive proximity detection system: - high signal to noise ratio (snr) - adjustable sensitivity - noise rejection filters - scanning method actively optimized to attenuate strongest noise frequencies - automatic calibration with optional user presets - dynamic threshold management adjusts sensitivity of sensor based on the level of environmental noise - constant press calibration tracks the expected offset when the sensor is pressed and adjusts the threshold to automatically achieve the best press/release behavior - user-defined ?minimum shift? values specify the lowest amount of signal change to activate a state transition. automatic thresholds never decrease below these settings. - automatic environmental compensation - stuck release mechanism ? no required external components ? low-power mode: highly configurable low-power mode - 1 ms to 4s sleep interval between sensor samples ? response time as low as 10 ms ? hardware error detection notifies if either sensor is shorted to v dd , v ss or the other sensor ? operating voltage range: - 1.8v to 3.3v ? operating temperature: - 40c to +85c package type the device is available in 8-lead soic and dfn packaging (see figure 1 ). figure 1: 8-pin diagram for mtch112 table 1: 8-pin so ic/dfn pinout description i/o 8-pin soic/dfn description v dd 1 power supply input mto/int 2 detect output (active-low) notification interrupt pin mti0 3 proximity/touch sensor input reset 4 device reset (active-low) sda 5 i 2 c? data scl 6 i 2 c? clock mti1/mtgrd0 7 proximity/touch sensor input active guard shield for mti0 v ss 8 ground reference mti0 reset v dd mto/int v ss mti1/mtgrd0 sda scl 1 2 3 4 5 6 8 soic, dfn 7 mtch112 dual-channel proximity/touch controller
mtch112 ds41668a-page 2 preliminary ? 2012 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ........................................................... 3 2.0 i 2 c? serial interface ............................................................................................................ ..................................................... 6 3.0 configuration registers ..................................................................................................... ...................................................... 13 4.0 electrical characteristics.................................................................................................. ........................................................ 25 5.0 packaging information ....................................................................................................... ...................................................... 34 index ........................................................................................................... ............... ......................................................................... 42 the microchip web site ......................................................................................................... .............................................................. 43 customer change notification service ........................................................................................... ..................................................... 43 customer support ............................................................................................................... ................................................................. 43 reader response ................................................................................................................ ................................................................ 44 product identification system ................................................................................................. ............................................................. 45 to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2012 microchip technology inc. preliminary ds41668a-page 3 mtch112 1.0 device overview the microchip mtouch? sensing mtch112 dual- channel proximity/touch controller provides an easy way to add proximity and/or touch sensor detection to any application. the device implements either two capacitive sensors or one sensor and one active guard driver. the optional device configuration through i 2 c? allows presets to be loaded in a production environ- ment. automatic calibration routines are used by default to choose the best options, so user configura- tion is not required. the mtch112 uses a sophisticated optimization algorithm to actively eliminate noise from the signal. while the noise level is being measured, the requirements for a proximity or touch detection are updated to reflect the degree of uncertainty in the readings. when a press is detected for the first time, the threshold is automatically calibrated to choose a smart threshold for the ?release? and next press. this creates a system that dynamically optimizes the signal- to-noise ratio for its environment. 1.1 automatic calibration it measures the amount of capacitance on each sensor pin and chooses the best of three possible waveforms to capture a capacitive measurement. it analyzes the two final settling voltages of the mti0 pin to more closely match the waveform on the mtgrd0 pin. the settling time for the waveform is calibrated to maximize sensitivity while minimizing the delay. this provides the best trade-off between signal and noise reduction. calibration results are stored in the on-board eeprom for faster recovery time on next power-up. these memory locations are accessible for read/write through the i 2 c communications to bypass the automatic calibration, if required. 1.2 communications ?i 2 c, slave mode 1.3 touch configurations ? mti0 is a dedicated capacitive sensor input ? mti1/mtgrd0 can either be another capacitive sensor or a guard driver for mti0 1.4 signal resolution ? 13 bits 1.5 pin description 1.5.1 mti0/mti1 connect the sensor to this input. an additional resistor of at least 4.7 k ? ? is recommended for best noise immunity. sensors up to 40 pf in capacitance are supported. sensors work best when the base capacitance is minimized. this will maximize the percentage change in capacitance when a finger is added to the circuit. 1.5.2 mtgrd0 when not scanning the pin for capacitance changes (mti1 functionality), the pin will be driven in phase with mti0 to minimize the voltage differential between the two pins. if the mtgrd0 pin?s trace surrounds the mti0 pin?s trace, the waveform on mtgrd0 will shield (or guard) mti0 from the effect of nearby noise sources or power planes. 1.5.3 mto the mtouch? sensing output pin is always driven to either v dd or v ss by the device. the mtch112 outcon register (see register 3-1 ) determines the behavior of the mto/int pin. the pin is always active- low, but the states in which this output occurs can be adjusted in the device?s outcon register. if no options are selected for output states, the mto pin acts as an interrupt to a master device. the mtch112 will pulse low for at least 1 ms if any state changes occur. further information must be determined by communicating through i 2 c with the device. 1.5.4 i 2 c ? serial data pin (sda) the sda pin is the serial data pin of the i 2 c interface. the sda pin is used to write or read the registers and configuration bits. the sda pin is an open-drain n-channel driver. therefore, it needs an external pull- up resistor from the v dd line to the sda pin. the rec- ommended resistance value is 1.5 k ? . except for start and stop conditions, the data on the sda pin must be stable during the high period of the clock. the high or low state of the sda pin can only change when the clock signal on the scl pin is low. refer to section 2.1.2 ?i2c operation? for more details on i 2 c serial interface communication.
mtch112 ds41668a-page 4 preliminary ? 2012 microchip technology inc. 1.5.5 i 2 c ? serial clock pin (scl) the scl pin is the serial clock pin of the i 2 c interface. the i 2 c interface only acts as a slave and the scl pin accepts only external serial clocks. the input data from the master device is shifted into the sda pin on the rising edges of the scl clock, and output from the device occurs at the falling edges of the scl clock. the scl pin is an open-drain n-channel driver. therefore, it needs an external pull-up resistor from the v dd line to the scl pin. the recommended resistance value is 1.5 k ? . refer to section 2.1.2 ?i2c operation? for more details on i 2 c serial interface communication. for more details, see figure 1 and tab l e 1 . 1.6 performance 1.6.1 proximity distance the maximum proximity distance will be highly dependent on the level of noise in the environment. to maximize the robustness of the controller, the noise level is measured and used to define how much shift is required in the signal before a reliable change in state can be determined. these values were taken in a low- noise environment. for more details, see figure 4-2 . 1.6.2 response time the response time is defined as the maximum amount of time delay between the sensor?s capacitance signif- icantly changing and the output being updated based on the outcon register?s configuration. this amount of time will be dependent on the lpcon register, as it determines how long the device will sleep after detecting no significant changes. the fastest response time can be achieved by setting the lpcon register for the minimum sleep time (see register 3-6 ). the controller only sleeps when idle and no changes in the environment are detected. if a change occurs, the device will operate without sleeping until the disturbance or capacitance is removed. for more details, see tab l e 4 - 2 . 1.6.3 hardware capacitive sensors are areas of metal connected through a series resistor of 4.7 k ? to one of the mtix pins. the following diagrams show some example layout configurations along with the recommended design guidelines. for more information about the design of capacitive sensors, see an1334, ? techniques for robust touch sensing design? . figure 1-1: two-sensor layouts ? example ground plane or noise source mtin1 mtin0 (1) (2) note: 1: 15 mm x 15 mm recommended. 2: maximize separation distance. 3: thickness of traces to pin: 0.1 ? 0.5 mm single layer pcb, two sensors (3) ground plane or noise source mtin1 mtin0 (1) (2) note: 1: 15 mm x 15 mm recommended. 2: maximize separation distance. 3: thickness of traces to pin: 0.1 ? 0.5 mm two layer pcb, two sensors (3)
? 2012 microchip technology inc. preliminary ds41668a-page 5 mtch112 figure 1-2: guard layouts ? example (1) (2) (3) front view back view (1) (2) (3) front view back view ground plane or adjacent sensor layout for thin pcbs layout for reverse-side shielding (min. pcb layer separation of 1.5mm is recommended.) ground plane or adjacent sensor ground plane or adjacent sensor (1) (2) (3) layout for single layer pcbs note: 1: 15 mm x 15 mm recommended. 2: >2 mm separation recommended. 3: >2 mm separation recommended. 4: thickness of traces to pin: 0.1 ? 0.5 mm >0.5 mm separation recommended. 5: thickness of guard around sensor: 1 mm mtgrd0 mtin0 mtgrd0 mtin0 mtgrd0 mtin0 mtgrd0 mtin0 mtgrd0 mtin0 (4) (4) (4)
mtch112 ds41668a-page 6 preliminary ? 2012 microchip technology inc. 2.0 i 2 c? serial interface this device supports the i 2 c serial protocol. the i 2 c module operates in slave mode, so it does not generate the serial clock. 2.1 overview this i 2 c interface is a two-wire interface. figure 2-1 shows a typical i 2 c interface connection. the i 2 c interface specifies different communication bit rates. these are referred to as standard, fast or high speed modes. the mtch112 device supports these three modes. the bit rates of these modes are: ? standard mode: bit rates up to 100 kbit/s ? fast mode: bit rates up to 400 kbit/s a device that sends data onto the bus is defined as a transmitter, and a device receiving data is defined as a receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions. the mtch112 device works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. communication is initiated by the master (microcontroller) which sends the start bit, followed by the slave address byte. the first byte transmitted is always the slave address byte, which contains the device code, the address bits and the r/w bit. figure 2-1: typical i 2 c? interface the i 2 c serial protocol only defines the field types, field lengths, timings, etc. of a frame. the frame content defines the behavior of the device. for details on the frame content (commands/data) refer to section 2.3 ?i2c commands? . refer to the nxp user manual (um10204_3) for more details on the i 2 c specifications. there was some concern as to the use of the acknowledge bit to indicate a command error condition. from section 3.6 of the nxp user manual (um10204_3, rev 03 - 19 june 2007) , the description states: ? the acknowledge takes place after every byte. the acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. all clock pulses including the acknowledge 9th clock pulse are generated by the master. ? from this we can state that the byte was not ? success- fully received ? since it is an invalid combination of address/command. 2.1.1 signal descriptions the i 2 c interface uses up to two pins (signals). these are: ? sda (serial data) (see section 1.5.4 ?i2c ? serial data pin (sda)? ) ? scl (serial clock) (see section 1.5.5 ?i2c ? serial clock pin (scl)? ) 2.1.2 i 2 c operation the mtch112 device i 2 c module is compatible with the nxp i 2 c specification. the following lists some of the module?s features: ? 7-bit slave addressing ? supports two clock rate modes: - standard mode, clock rates up to 100 khz - fast mode, clock rates up to 400 khz ? support multi-master applications the i 2 c 10-bit addressing mode is not supported. the nxp i 2 c specification only defines the field types, field lengths, timings, etc. of a frame. the frame content defines the behavior of the device. the frame content for this device is defined in section 2.3 ?i2c commands? . i 2 c bit states and sequence figure 2-7 shows an i 2 c 8-bit transfer sequence, while figure 2-8 shows the bit definitions. the serial clock is generated by the master. the following definitions are used for the bit states: ? start bit (s) ? data bit ? acknowledge (a) bit (driven low) / no acknowledge (a ) bit (not driven low) ? repeated start bit (sr) ? stop bit (p) start bit the start bit (see figure 2-2 ) indicates the beginning of a data transfer sequence. the start bit is defined as the sda signal falling when the scl signal is high. figure 2-2: start bit scl scl mtch112 sda sda host controller typical i 2 c? interface connections sda scl s 1st bit 2nd bit
? 2012 microchip technology inc. preliminary ds41668a-page 7 mtch112 data bit the sda signal may change state while the scl signal is low. while the scl signal is high, the sda signal must be stable (see figure 2-3 ). figure 2-3: data bit acknowledge (a) bit the a bit (see figure 2-4 ) is typically a response from the receiving device to the transmitting device. depending on the context of the transfer sequence, the a bit may indicate different things. typically, the slave device will supply an a response after the start bit and 8 data bits have been received. an a bit has the sda signal low. figure 2-4: acknowledge waveform not a (a ) response the a bit has the sda signal high. table 2-1 shows some of the conditions where the slave device will issue a not a (a ). if an error condition occurs (such as an a instead of a), then a start bit must be issued to reset the command state machine. sda scl data bit 1st bit 2nd bit a 8 d0 9 sda scl table 2-1: mtch112 a / a responses event acknowledge bit response comment general call a slave address valid a slave address not valid a communication during eeprom write cycle a the device will nack after a valid write sequence until all bytes are executed. bus collision n/a treated as ?don?t care? if the collision occurs on the start bit. otherwise, i 2 c? resets.
mtch112 ds41668a-page 8 preliminary ? 2012 microchip technology inc. repeated start bit the repeated start bit (see figure 2-5 ) indicates that the current master device wishes to continue commu- nicating with the current slave device without releasing the i 2 c bus. the repeated start condition is the same as the start condition, except that the repeated start bit follows a start bit (with the data bits + a bit) and not a stop bit. the start bit is the beginning of a data transfer sequence and is defined as the sda signal falling when the scl signal is high. figure 2-5: repeat start condition waveform stop bit the stop bit (see figure 2-6 ) indicates the end of the i 2 c data transfer sequence. the stop bit is defined as the sda signal rising when the scl signal is high. a stop bit resets the i 2 c interface of the mtch112 device. figure 2-6: stop condition receive or transmit mode 2.1.2.1 clock stretching clock stretching is something that the receiving device can do to allow additional time to respond to the data that has been received. this device will stretch the clock signal (scl) after a write command to allow the eeprom write operation to complete. 2.1.2.2 aborting a transmission if any part of the i 2 c transmission does not meet the command format, it is aborted. this can be intentionally accomplished with a start or stop condition. this is done so that noisy transmissions (usually an extra start or stop condition) are aborted before they corrupt the device. figure 2-7: typical 8-bit i 2 c? waveform format figure 2-8: i 2 c? data states and bit sequence note 1: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low-to-high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. sda scl sr = repeated start 1st bit scl sda a / a p 1st bit sda scl s 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit p a / a scl sda start condition stop condition data allowed to change data or a valid
? 2012 microchip technology inc. preliminary ds41668a-page 9 mtch112 2.1.2.3 slope control this device does not implement slope control on the sda output. 2.1.2.4 device addressing the address byte is the first byte received following the start condition from the master device. the full 7 bits of the i 2 c slave address is user programmable. the default address is ? 1110011 ?. figure 2-9 shows the i 2 c slave address byte format, which contains the seven address bits and a read/ write (r/w ) bit. figure 2-9: slave address bits in the i 2 c? control byte start bit read/write bit address byte r/w ack acknowledge bit slave address a6 a5 a4 a3 slave address (7 bits) a2 a1 a0 note 1: address bits (a6:a0) can be reprogrammed by the customer. 1 1 10 01 1 a0 address note 1
mtch112 ds41668a-page 10 preliminary ? 2012 microchip technology inc. 2.2 device commands this section documents the commands that the device supports. the commands can be grouped into the following categories: ? write memory ? read memory table 2-2: reset to factory settings desc. start device write protection reset command checksum (1) stop example s 0xe6 0x55 0xaa 0x00 0xff 0x00 p notes ? write required factory settings ?? note 1: checksum is the binary xor of all bytes except the device address. table 2-3: write to register desc. start device write protection register value checksum (1) stop example s 0xe6 0x55 0xaa 0x01 0x01 0xff p notes ? write required outcon ??? note 1: checksum is the binary xor of all bytes except the device address. table 2-4: read from register desc. start device register restart device data stop start device checksum (1) stop example s0xe6 0x80 s 0xe7 ? ps0xe7 0xzz p notes write state read ? read ? note 1: read checksum is the binary xor of all bytes in the data column. this is an optional step. the checksum can be ignored if the master does not wish to read it.
? 2012 microchip technology inc. preliminary ds41668a-page 11 mtch112 2.3 i 2 c commands the i 2 c protocol does not specify how commands are formatted, so this section specifies the mtch112 device?s i 2 c command formats and operation. the commands can be grouped into the following categories: ? write commands ? read commands the supported commands are shown in table 2-2 , table 2-3 and ta bl e 2 - 4 . 2.3.1 write commands write commands are used to transfer data to the desired memory location (from the host controller). the write command form writes the device address, 0x55, 0xaa, the data address, the value to write and an xor checksum. 2.3.2 read commands the read command format writes two bytes, the control byte and the desired memory address byte, and then has a restart condition. then a second control byte is transmitted, but this control byte indicates a i 2 c read operation (r/w bit = 1 ). 2.3.3 reset to factory settings command resetting the device to factory settings is equivalent to writing the value 0xff to the data address 0x00 . the proper write protocol must be followed, including the address byte with the write bit set, 0x55, 0xaa and a binary xor checksum at the end. 2.3.4 aborting a command transmission a restart or stop condition in an expected data bit posi- tion will abort the current command sequence and data will not be written to the mtch112. write commands are automatically aborted if the binary xor checksum is not valid. 2.3.5 write command (normal and high voltage) the format of the command is shown in figure 2-10 . the mtch112 generates the a/a bits. a write command will only start a write cycle after a properly formatted write command has been received and the stop condition has occurred. 2.3.5.1 writing to memory the protocol allows for a variable number of bytes to be written to the device at a time. once the stop bit has been sent, a time delay is required while the eeprom write cycle stores each data byte. while the device is writing the eeprom, the address will be changed (by toggling the least significant address bit of the device, then toggling back once finished) to prevent accidental double writes. an error may occur if a write command is sent while the eeprom is still storing the previous bytes. while the writing is being performed, reads to the normal device address will result in a nack. figure 2-10 shows the waveform for a single write. figure 2-10: write random address command sa s 0 ad ad ad ad ad a a 4 5 6 7 i 2 c? slave address device memory address write bit 3 a c cccc ccc ap write data (optional) 0 1 2 3 4 5 6 7 d dddd ddd 0 1 2 3 4 5 6 7 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 ad 2 ad 1 ad 0 0 1 0 1 0 1 0 1 a 1 0 1 01010 a required write unlock sequence a d dddd ddd 0 1 2 3 4 5 6 7 write data xor checksum
mtch112 ds41668a-page 12 preliminary ? 2012 microchip technology inc. 2.3.6 read command the read command can be issued to all memory locations. the format of the command (see figure 2-11 ) includes the start condition, i 2 c control byte (with r/w bit set to 0 ), a bit, the data address byte, a bit, followed by a repeated start bit, i 2 c control byte (with r/w bit set to 1 ) and the mtch112 device transmitting the requested data bytes one at a time until the master sends a stop condition. the i 2 c control byte requires the r/w bit equal to a logic one (r/w = 1 ) to generate a read sequence. the memory location read will start at the requested data address and automatically increments by one after each byte request. notice that the read operation packets do not include the 0x55 and 0xaa write protection bytes. after the stop condition has been received, if a start condition is followed by the device address, the device will send the xor checksum of the data bytes from the previous read packet. this allows the checksum to be ignored by the master, if desired. read operations initially include the same address byte sequence as the write sequence (shown in figure 2-10 ). this sequence is followed by another control byte (including the start condition and acknowledge) with the r/w bit equal to a logic one (r/w = 1 ) to indicate a read. the mtch112 will then transmit the data contained in the addressed register. this is followed by the master generating an a bit in preparation for more data, or an a bit followed by a stop. the sequence is ended with the master generating a stop or restart condition. figure 2-11 shows the waveforms for a single read. 2.3.6.1 ignoring an i 2 c transmission and ?falling off? the bus the mtch112 device expects to receive complete, valid i 2 c commands and will assume any command not defined as a valid command is due to a bus corruption and will enter a passive high condition on the sda signal. all signals will be ignored until the next valid start condition and control byte are received. figure 2-11: random read command stop bit ad ad ad ad ad 1 2 3 4 i 2 c? slave address data memory address d ddd d d dd a 1 d dddd ddd p 1a read bit read data byte (optional) note 1: master device is responsible for a/a signal. if a a signal occurs, the mtch112 will abort this transfer and release the bus. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 s sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 i 2 c slave address write bit 0 a s asr repeated start bit sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 1 read bit xor checksum p ad ad 6 7 ad 5 read data byte i 2 c slave address c 7 c 6 c 5 c 4 c 3 c 2 c 1 a
? 2012 microchip technology inc. preliminary ds41668a-page 13 mtch112 3.0 configuration registers the registers in the mtch112 have been organized in two groups: the configuration registers and the output registers. the output registers are in the 0x80 (and higher) address range and are read-only. they provide the current sensor data for each input. the configura- tion registers are both writable and readable. they show the current scan options and define the systems behavior. to restore the configuration registers to their default states and force a recalibration of the sensors, perform a write operation of 0xff to address 0x00 . 3.1 output control register (outcon) this register contains the control bits for the mto/int pin to determine its behavior. if multiple bits in this register are set, the states they represent are ord before the output is determined. for example, if the s1boe and s0boe bits are set, the mto pin will output low if either mti0 or mti1 detect a button touch. if the s1poe and s0poe bits are set, the mto pin will output low if either mti0 or mti1 make a proximity detection. if none of the bits are set, the pin will perform as a 1 ms pulsed interrupt pin for the i 2 c master. (see register 3-1 ) register 3-1: outcon: output control register u-0 u-0 u-0 u-0 r/w-0/u r/w-0/u r/w-1/u r/w-1/u ? ? ? ?s1poe (1) s0poe (1) s1boe (1) s0boe (1) bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-4 unimplemented: read as ? 0 ? bit 3 s1poe: sensor 1 proximity output enable bit 1 = output pin activates when sensor 1 makes a proximity detection 0 = output pin does not change based on sensor 1?s proximity detection bit 2 s0poe: sensor 0 proximity output enable bit 1 = output pin activates when sensor 0 makes a proximity detection 0 = output pin does not change based on sensor 0?s proximity detection bit 1 s1boe: sensor 1 button output enable bit 1 = output pin activates when sensor 1 makes a button press detection 0 = output pin does not change based on sensor 1?s button press detection bit 0 s0boe: sensor 0 button output enable bit 1 = output pin activates when sensor 0 makes a button press detection 0 = output pin does not change based on sensor 0?s button press detection note 1: if all output enable bits are ? 0 ?, the output pin will behave as a wake-up signal to the master. it will be set active-low whenever new data becomes available.
mtch112 ds41668a-page 14 preliminary ? 2012 microchip technology inc. 3.2 calibration control registers (calconx) this register contains the calibration information for mtix. it stores the chosen waveform type and whether or not the calibration has been completed. to recali- brate a sensor, clear its respective sxcal bit in the calconx register (see register 3-2 and register 3-3 ). register 3-2: calcon0: sensor 0?s calibration co ntrol register r/w-0/u r/w-0/u u-0 u-0 u-0 u-0 r/w-0/u u-1 s0ws<1:0> ? ? ? ?s0cal ? bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-6 s0ws<1:0>: sensor 0 waveform selection bits 00 = normal mtouch? sensing cvd waveform 01 = double mtouch? sensing cvd waveform 10 = half mtouch? sensing cvd waveform 11 = reserved. results in double mtouch? sensing cvd waveform bit 5-2 unimplemented: read as ? 0 ? bit 1 s0cal: sensor 0 calibrated bit 1 = sensor 0 calibration complete 0 = new sensor 0 calibration requested bit 0 unimplemented: read as ? 0 ? register 3-3: calcon1: sensor 1?s calibration co ntrol register r/w-0/u r/w-0/u u-0 u-0 u-0 u-0 r/w-0/u r/w-1/u s1ws<1:0> ? ? ? ? s1cal s1en bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-6 s1ws<1:0>: sensor 1 waveform selection bits 00 = normal mtouch? sensing cvd waveform 01 = double mtouch? sensing cvd waveform 10 = half mtouch? sensing cvd waveform 11 = reserved. results in double mtouch? sensing cvd waveform bit 5-2 unimplemented: read as ? 0 ? bit 1 s1cal: sensor 1 calibrated bit 1 = sensor 1 calibration complete 0 = new sensor 1 calibration requested bit 0 s1en: sensor 1 enabled bit 1 = sensor 1 is enabled. scanning and decoding active. 0 = sensor 1 is disabled. no scanning or decoding is performed.
? 2012 microchip technology inc. preliminary ds41668a-page 15 mtch112 3.3 adc acquisition time registers (adacqx) this stores the settling delay time for the cvd waveform. this value is part of the recalibration process and will be overwritten if the sxcal bit is cleared (see register 3-4 and register 3-5 ). register 3-4: adacq0: sensor 0?s acquisition delay u-0 u-0 u-0 r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u ? ? ? s0acq<4:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-5 unimplemented: read as ? 0 ? bit 4-0 s0acq<4:0>: sensor 0 acquisition delay bits register 3-5: adacq1: sensor 1?s acquisition delay u-0 u-0 u-0 r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u ? ? ? s1acq<4:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-5 unimplemented: read as ? 0 ? bit 4-0 s1acq<4:0>: sensor 1 acquisition delay bits
mtch112 ds41668a-page 16 preliminary ? 2012 microchip technology inc. 3.4 low-power control register (lpcon) this register provides the low-power options for the mtch112. it determines how long the device will sleep when no detections have been made, and how fast the internal oscillator will run. if the clksel bit is set, the valid v dd operating range will decrease. see the bit description in register 3-6 for more information. register 3-6: lpcon: lo w-power control register u-0 u-0 r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-1/u r/w-1/u ? ? sleep<4:0> clksel bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-6 unimplemented: read as ? 0 ? bit 5-1 sleep<4:0>: sleep duration between scans when inactive 00000 = 1 ms, typical sleep duration 00001 = 2 ms, typical sleep duration 00010 = 4 ms, typical sleep duration 00011 = 8 ms, typical sleep duration 00100 = 16 ms, typical sleep duration 00101 = 32 ms, typical sleep duration 00110 = 64 ms, typical sleep duration 00111 = 128 ms, typical sleep duration 01000 = 256 ms, typical sleep duration 01001 = 512 ms, typical sleep duration 01010 = 1 sec, typical sleep duration 01011 = 2 sec, typical sleep duration 01100 = 4 sec, typical sleep duration 01101 = 8 sec, typical sleep duration 01110 = 16 sec, typical sleep duration 01111 = 32 sec, typical sleep duration 10000 = 64 sec, typical sleep duration 10001 = 128 sec, typical sleep duration 10010 = 256 sec, typical sleep duration 10011 = reserved. results in 1 ms sleep duration. ... 11111 = reserved. results in 1 ms sleep duration. bit 0 clksel: oscillator selection bit 1 = internal oscillator runs at 32 mhz decreases response time increases power consumption valid v dd operating range when selected is 2.5v-3.6v 0 = internal oscillator runs at 16 mhz decreases response time increases power consumption valid v dd operating range when selected is 1.8v-3.6v
? 2012 microchip technology inc. preliminary ds41668a-page 17 mtch112 3.5 press threshold register (press_thresh) the register stores the minimum shift amount of the signal away from the baseline that is required to activate a sensor as ? touched ?. the real-time threshold of the sensor is handled internally, based on current noise levels and the expected press amount. this value simply creates a lower bound. it is not mandatory unless the user wishes to ensure that the sensor is not too sensitive in low-noise environments (see register 3-7 ). 3.6 proximity threshold register (prox_thresh) this register is identical to the press threshold register, except that it relates to the proximity detection. increase this value to decrease the sensitivity of the sensor in low-noise environments (see register 3-8 ). register 3-7: press_thresh: press threshold register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u press_thsh<7:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-0 press_thsh<7:0>: absolute minimum press threshold register 3-8: prox_thresh: proximity threshold register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u prox_thsh<7:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-0 prox_thsh<7:0>: absolute minimum proximity threshold
mtch112 ds41668a-page 18 preliminary ? 2012 microchip technology inc. 3.7 16-bit time-out register (timeout_l and timeout_h) this set of registers determines how long the ?detected? state is able to remain activated before automatically being reset to a non-detected state. it also determines how long after no changes in the environment have occurred before setting the controller to its idle state. when in idle state, the system will sleep (see register 3-6 ) between each reading (see register 3-9 and register 3-10 ). register 3-9: timeout_l: time-o ut counter, low byte register r/w-1/u r/w-1/u r/w-1/u r/w-1/u r/w-1/u r/w-1/u r/w-1/u r/w-1/u timeout<7:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-0 timeout<7:0>: time-out counter reload value, low byte register 3-10: timeout_h: time-o ut counter, high byte register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-1/u timeout<15:8> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-0 timeout<15:8>: time-out counter reload value, high byte
? 2012 microchip technology inc. preliminary ds41668a-page 19 mtch112 3.8 i 2 c address register (i 2 caddr) this register determines the i 2 c address of the slave. after writing to this register, command immediately should begin using the new address value (see register 3-11 ). register 3-11: i 2 caddr: i 2 c? address register r/w-1/u r/w-1/u r/w-1/u r/w-0/u r/w-0/u r/w-1/u r/w-1/u u-1 i 2 caddr<7:1> ? bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-1 i 2 caddr<7:1>: i 2 c address for communication with the mtch112. bit 0 unimplemented: read as ? 0 ?
mtch112 ds41668a-page 20 preliminary ? 2012 microchip technology inc. 3.9 state register (state) this register is read-only. it contains the current touch and proximity state of mti0 and mti1, and provides error information if a short is detected on any mtix pin to v dd , v ss or the other mtix pin (see register 3-12 ). register 3-12: state: current sensor state register u-0 r-0/x r-0/x r-0/x r-0/x r-0/x r-0/x r-0/x ? errstate<2:0> s1ps s0ps s1bs s0bs bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7 unimplemented: read as ? 0 ? bit 6-4 errstate<2:0>: error status information bits 000 = both sensors floating correctly 001 = sensor 0 is shorted to v dd 010 = sensor 1 is shorted to v dd 011 = sensor 0 is shorted to v ss 100 = sensor 1 is shorted to v ss 101 = sensors are shorted together 110 = reserved 111 = reserved bit 3 s1ps: sensor 1 proximity status bit 1 = proximity detected on sensor 1 0 = no proximity detected on sensor 1 bit 2 s0ps: sensor 0 proximity status bit 1 = proximity detected on sensor 0 0 = no proximity detected on sensor 0 bit 1 s1bs: sensor 1 button status bit 1 = button press detected on sensor 1 0 = no button press detected on sensor 1 bit 0 s0bs: sensor 0 button status bit 1 = button press detected on sensor 0 0 = no button press detected on sensor 0
? 2012 microchip technology inc. preliminary ds41668a-page 21 mtch112 3.10 reading registers (readingxl and readingxh) these registers contain the current raw value of the mtix pins. they are 13-bit values, but it is recommended to treat them as 16-bit values to more easily support future designs (see register 3-13 to register 3-16 ). register 3-13: reading0l: sensor 0 reading value, low byte r-x r-x r-x r-x r-x r-x r-x r-x reading0l<7:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-0 reading0l<7:0>: sensor 0 current reading value, low byte register 3-14: reading0h: sensor 0 reading value, high byte u-0 u-0 u-0 r-x r-x r-x r-x r-x ? ? ? reading0h<4:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-5 unimplemented: read as ? 0 ? bit 4-0 reading0h<4:0>: sensor 0 current reading value, high byte register 3-15: reading1l: sensor 1 reading value, low byte r-x r-x r-x r-x r-x r-x r-x r-x reading1l<7:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-0 reading1l<7:0>: sensor 1 current reading value, low byte
mtch112 ds41668a-page 22 preliminary ? 2012 microchip technology inc. 3.11 baseline registers (baselinexl and baselinexh) these registers contain the current baseline value of the mtix pins. they are 13-bit values, but it is recommended to treat as unsigned 16-bit values to more easily support future designs (see register 3-17 to register 3-20 ). register 3-16: reading1h: sensor 1 reading value, high byte u-0 u-0 u-0 r-x r-x r-x r-x r-x ? ? ? reading1h<4:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-5 unimplemented: read as ? 0 ? bit 4-0 reading1h<4:0>: sensor 1 current reading value, high byte register 3-17: baseline0l: sensor 0 baseline value, low byte r-x r-x r-x r-x r-x r-x r-x r-x baseline0l<7:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-0 baseline0l<7:0>: sensor 0 current baseline value, low byte register 3-18: baseline0h: sensor 0 baseline value, high byte u-0 u-0 u-0 r-x r-x r-x r-x r-x ? ? ? baseline0h<4:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-5 unimplemented: read as ? 0 ? bit 4-0 baseline0h<4:0>: sensor 0 current baseline value, high byte
? 2012 microchip technology inc. preliminary ds41668a-page 23 mtch112 register 3-19: baseline1l: sensor 1 baseline value, low byte r-x r-x r-x r-x r-x r-x r-x r-x baseline1l<7:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-0 baseline1l<7:0>: sensor 1 current baseline value, low byte register 3-20: baseline1h: sensor 1 baseline value, high byte u-0 u-0 u-0 r-x r-x r-x r-x r-x ? ? ? baseline1h<4:0> bit 7 bit 0 legend: r = readable bit u = unimplemented bit, read as ?0? u = bit is unchanged -n/n = factory setting value/value after all resets ?1? = bit is set ?0? = bit is cleared w = writable bit bit 7-5 unimplemented: read as ? 0 ? bit 4-0 baseline1h<4:0>: sensor 1 current baseline value, high byte
mtch112 ds41668a-page 24 preliminary ? 2012 microchip technology inc. table 3-1: register mapping address name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 ? ? ? ? ? ? ? ? ? 0x01 outcon ? ? ? ? s1poe s0poe s1boe s0boe 0x02 calcon0 s0ws ? ? ? ? s0cal ? 0x03 calcon1 s1ws ? ? ? ? s1cal s1en 0x04 adacq0 s0acq<4:0> 0x05 adacq1 s1acq<4:0> 0x06 lpcon sleep<4:0> clksel 0x07 press_thresh press_thsh<7:0> 0x08 prox_thresh prox_thsh<7:0> 0x09 timeout_l timeout<7:0> 0x0a timeout_h timeout<15:8> 0x0b i 2 caddr i 2 caddr<7:1> ? 0x0c ? ? ? ? ? ? ? ? ? 0x0d ? ? ? ? ? ? ? ? ? 0x0e ? ? ? ? ? ? ? ? ? 0x0f ? ? ? ? ? ? ? ? ? 0x80 state ? errstate<2:0> s1ps s0ps s1bs s0bs 0x81 reading0l reading0l<7:0> 0x82 reading0h ? ? ? reading0h<4:0> 0x83 reading1l reading1l<7:0> 0x84 reading1h ? ? ? reading1h<4:0> 0x85 baseline0l base0l<7:0> 0x86 baseline0h ? ? ? base0h<4:0> 0x87 baseline1l base1l<7:0> 0x88 baseline1h ? ? ? base1h<4:0>
? 2012 microchip technology inc. preliminary ds41668a-page 25 mtch112 4.0 electrical specifications absolute maximum ratings (?) ambient temperature under bias................................................................................................. ...... -40c to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on v dd with respect to v ss .................................................................................................... -0.3v to +4.0v voltage on mclr with respect to vss ................................................................................................. -0.3v to +9.0v voltage on all other pins with respect to v ss ........................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... 800 mw maximum current out of v ss pin, -40c ? t a ? +85c for industrial................................................................. 85 ma maximum current into v dd pin, -40c ? t a ? +85c for industrial.................................................................... 80 ma clamp current, i k (v pin < 0 or v pin > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????? 20 ma maximum output current sunk by any i/o pin..................................................................................... ............... 25 ma maximum output current sourced by any i/o pin .................................................................................. ............ 25 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? ? i oh } + ? {(v dd ? v oh ) x i oh } + ? (v o l x i ol ). ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
mtch112 ds41668a-page 26 preliminary ? 2012 microchip technology inc. figure 4-1: voltage frequency graph, -40c ? t a ?? +125c note 1: the shaded region indicates the permissible combinations of voltage and frequency. 1.8 0 2.5 frequency (mhz) v dd (v) 32 16 3.6 4.1 dc characteristics: mtch112 mtch112 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param. no. sym. characteristic min. typ? max. units conditions d001 v dd supply voltage 1.8 2.5 ? ? 3.6 3.6 v v clksel = 0 clksel = 1 d002* v dr ram data retention voltage (1) 1.5 ? ? v device in sleep mode v por * power-on reset release voltage ?1.6? v v porr * power-on reset rearm voltage ? 0.8 ? v device in sleep mode d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data.
? 2012 microchip technology inc. preliminary ds41668a-page 27 mtch112 table 4-1: current consumption clksel sleep (s) 1.8v 3.0v clksel sleep (s) 3.0v 3.6v typ. (ua) typ. (ua) typ. (ua) typ. (ua) 16 mhz 0 640 990 32 mhz 0 1952 2350 0.001 580 900 0.001 1780 2140 0.002 540 830 0.002 1630 1970 0.004 460 710 0.004 1400 1690 0.008 360 560 0.008 1090 1320 0.016 250 390 0.016 760 915 0.032 160 240 0.032 470 570 0.064 89 140 0.064 270 320 0.128 48 74 0.128 150 170 0.256 25 38 0.256 75 91 0.512 13 20 0.512 39 46 1 6.8 11 1 20 24 2 3.6 5.5 2 10 12 4 1.9 3.0 4 56 8 1.1 1.8 8 33 16 0.7 1.1 16 1.7 2 32 0.5 0.8 32 11 64 0.4 0.7 64 0.8 0.9 128 0.3 0.6 128 0.7 0.7 256 0.3 0.5 256 0.6 0.6 table 4-2: response time (1) clksel min. max. 1 (32 mhz) 20 ms 20 ms + lpcon 0 (16 mhz) 40 ms 40 ms + lpcon note 1: it assumes low and/or consistent environmental noise. response times increase in high and/or erratic noise conditions.
mtch112 ds41668a-page 28 preliminary ? 2012 microchip technology inc. figure 4-2: maximum proximity distance vs. sensor diameter figure 4-3: por and por rearm with slow rising v dd 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 1 1.5 2 2.5 3 distance (inch) round pad diameter (inch) v dd v por v porr v ss v ss npor (1) t por (3) por rearm note 1: when npor is low, the device is held in reset. 2: t por 1 ? s typical. 3: t vlow 2.7 ? s typical. t vlow (2)
? 2012 microchip technology inc. preliminary ds41668a-page 29 mtch112 4.2 dc characteristics: mtch112-i/e dc characteristics standard operating conditions (unless otherwise stated) operating temperature-40c ? t a ? +85c for industrial param no. sym. characteristic min. typ? max. units conditions v il input low voltage i/o port: d030a with ttl buffer ? ? 0.15 v d d v1.8v ? v dd ? 4.5v d031 with i 2 c? levels ? ? 0.3 v dd v d032 mclr ??0.2v dd v v ih input high voltage i/o ports: ? ? d040a with ttl buffer 0.25 v dd + 0.8 ??v1.8v ? v dd ? 4.5v d041 with i 2 c? levels 0.7 v dd ??v d042 mclr 0.8 v dd ??v i il input leakage current (1) d060 i/o ports ? ? 5 5 125 1000 na na v ss ? v pin ? v dd , pin at high-impedance at 85c 125c d061 mclr (2) ? 50 200 na v ss ? v pin ? v dd at 85c v ol output low voltage (3) d080 i/o ports ? ?0.6v i ol = 6 ma, v dd = 3.3v i ol = 1.8 ma, v dd = 1.8v v oh output high voltage (3) d090 i/o ports v dd - 0.7 ? ? v i oh = 3 ma, v dd = 3.3v i oh = 1 ma, v dd = 1.8v capacitive loading specs on output pins d101a* c io all i/o pins ? ? 50 pf * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: negative current is defined as current sourced by the pin. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: including osc2 in clkout mode.
mtch112 ds41668a-page 30 preliminary ? 2012 microchip technology inc. figure 4-4: load conditions table 4-3: clkout and i/o timing parameters 4.3 memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions data eeprom memory d116 e d byte endurance 100k ? ? e/w -40 ? c to +85 ? c d117 v drw v dd for read/write v ddmin ?v ddmax v d118 t dew erase/write cycle time ? 4.0 5.0 ms d119 t retd characteristic retention 20 ? ? year provided no other specifications are violated ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v ss c l legend: c l = 50 pf for all pins, 15 pf for osc2 output load condition pin standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions os18* tior port output rise time ? ? 90 55 140 80 ns v dd = 1.8v v dd = 3.0-5.0v os19* tiof port output fall time ? ? 60 44 80 60 ns v dd = 1.8v v dd = 3.0-5.0v * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25 ? c unless otherwise stated.
? 2012 microchip technology inc. preliminary ds41668a-page 31 mtch112 figure 4-5: brown-out rese t timing and characteristics table 4-4: reset, watchdog timer, oscill ator start-up timer, power-up timer and brown-out reset parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 30 t mc l reset pulse width (low) 2 5 ? ? ? ? ? s ? s v dd = 3.3-5v, -40c to +85c v dd = 3.3-5v 31 t wdtlp watchdog timer time-out period 10 16 27 ms v dd = 3.3v-5v, 1:16 prescaler used 33* t pwrt power-up timer period 40 65 140 ms 34* t ioz i/o high-impedance from reset low or watchdog timer reset ??2.0 ? s 35 v bor brown-out reset voltage 1.80 1.9 2.05 v borv=1.9v 37* v hyst brown-out reset hysteresis 0 25 50 mv -40c to +85c 38* t bordc brown-out reset dc response time 0140 ? sv dd ? v bor * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v bor v dd (device in brown-out reset) (device not in brown-out reset) 33 reset (due to bor) v bor and v hyst 37
mtch112 ds41668a-page 32 preliminary ? 2012 microchip technology inc. figure 4-6: i 2 c? bus start/stop bits timing figure 4-7: i 2 c? bus data timing note : refer to figure 4-4 for load conditions. sp91 sp92 sp93 sclx sdax start condition stop condition sp90 note: refer to figure 4-4 for load conditions. sp90 sp91 sp92 sp100 sp101 sp103 sp106 sp107 sp109 sp109 sp110 sp102 sclx sdax in sdax out
? 2012 microchip technology inc. preliminary ds41668a-page 33 mtch112 table 4-5: i 2 c? bus data requirements param. no. symbol characteristic min. max. units conditions sp100* t high clock high time 400 khz mode 0.6 ? ? s device must operate at a minimum of 10 mhz sspx module 1.5t cy ?? sp101* t low clock low time 400 khz mode 1.3 ? ? s device must operate at a minimum of 10 mhz sp102* t r sdax and sclx rise time 400 khz mode 20 + 0.1c b 300 ns c b is specified to be from 10-400 pf sp103* t f sdax and sclx fall time 400 khz mode 20 + 0.1c b 250 ns c b is specified to be from 10-400 pf sp106* t hd : dat data input hold time 400 khz mode 0 0.9 ? s sp107* t su : dat data input setup time 400 khz mode 100 ? ns sp109* t aa output valid from clock 400 khz mode ? ? ns sp110* t buf bus free time 400 khz mode 1.3 ? ? s time the bus must be free before a new transmission can start sp111 c b bus capacitive loading ? 400 pf * these parameters are characterized but not tested.
mtch112 ds41668a-page 34 preliminary ? 2012 microchip technology inc. 5.0 packaging information 5.1 package marking information 8-lead soic (3.90 mm) example nnn mtch112 /sn1243 017 8-lead dfn (3x3x0.9 mm) example xxxx nnn yyww pin 1 pin 1 mft0 1243 017 * standard pic ? device marking consists of microchip part number, year code, week code, and traceability code. for pic device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 2012 microchip technology inc. preliminary ds41668a-page 35 mtch112 5.2 package details the following sections give the technical details of the packages. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mtch112 ds41668a-page 36 preliminary ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. preliminary ds41668a-page 37 mtch112
mtch112 ds41668a-page 38 preliminary ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. preliminary ds41668a-page 39 mtch112 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mtch112 ds41668a-page 40 preliminary ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. preliminary ds41668a-page 41 mtch112 appendix a: data sheet revision history revision a (11/2012) initial release of this data sheet.
mtch112 ds41668a-page 42 preliminary ? 2012 microchip technology inc. index symbols i2c hardware interface ......................................................... 6 numerics 16-bit time-out register (timeout_l and timeout_h) . 18 a absolute maximum ratings ................................................ 25 adc acquisition time registers (adacqx) ....................... 15 b baseline registers (baselinexl and baselinexh) ....... 22 brown-out reset (bor) specifications.............................................................. 31 timing and characteristics ......................................... 31 c calibration control registers (calconx) .......................... 14 configuration registers....................................................... 13 customer change notification service ............................... 43 customer notification service............................................. 43 customer support ............................................................... 43 d dc characteristics industrial ..................................................................... 29 mtch112.................................................................... 26 device overview ................................................................... 3 e electrical specifications ...................................................... 25 errata .................................................................................... 2 f features ................................................................................ 1 i i2c address register (i2caddr)....................................... 19 i2c? communications and protocol .................................... 6 internet address.................................................................. 43 l low power control register (lpcon)................................ 16 m microchip internet web site ................................................ 43 o oscillator start-up timer (ost) specifications.............................................................. 31 output control register (outcon) ................................... 13 p package type ....................................................................... 1 packaging soic, dfn.................................................................. 35 packaging information ........................................................ 34 power-up timer (pwrt) specifications.............................................................. 31 press threshold register (press_thresh) ................... 17 proximity threshold register (prox_thresh)................ 17 r reader response ............................................................... 44 reading registers (readingxl and readingxh).......... 21 register mapping................................................................ 24 revision history.................................................................. 41 s state register (state) ...................................................... 20 t timing diagrams brown-out reset (bor).............................................. 31 i 2 c bus data............................................................... 32 timing requirements i 2 c bus data............................................................... 33 w www address ................................................................... 43 www, on-line support ....................................................... 2
? 2012 microchip technology inc. preliminary ds41668a-page 43 mtch112 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
mtch112 ds41668a-page 44 preliminary ? 2012 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41668a mtch112 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2012 microchip technology inc. preliminary ds41668a-page 45 mtch112 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: mtch112 tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1) temperature range: i= -40 ? c to +85 ? c (industrial) package: (2) sn = soic mf = dfn pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) mtch112 - i/mf industrial temperature, dfn package note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. 2: for other small form-factor package availability and marking information, please visit www.microchip.com/packaging or contact your local sales office. [x] (1) tape and reel option -
mtch112 ds41668a-page 46 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds41668a-page 47 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, application maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620767108 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications c ontained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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